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 SSM7002DGU
Dual N-channel Enhancement-mode Power MOSFETs
PRODUCT SUMMARY
BVDSS R DS(ON) ID
DESCRIPTION
The SSM7002DG acheives fast switching performance with low gate charge without a complex drive circuit. It is suitable for low voltage applications such as DC/DC converters and general load-switching circuits. The SSM7002DGU is supplied in a RoHS-compliant SOT-363 package, which is widely used where board space is critical and a small footprint is required.
50V 3 250mA
Pb-free; RoHS-compliant SOT-363
G1 S1
D2
D1
SOT-363
S2
G2
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VGS ID Parameter Drain-source voltage Gate-source voltage Continuous drain current Pulsed drain current
1,2
3
3 ,
Value 50 20 T A = 25C 250
Units V V mA
ISD
IDM PD TSTG TJ
Source-drain diode current
Total power dissipation , TA = 25C TA = 75C Storage temperature range Operating junction temperature range
115
1.0 200 120 -55 to 150 -55 to 150
mA
A mW mW C C
THERMAL CHARACTERISTICS
Symbol RJA Parameter Maximum thermal resistance, junction-ambient
3
Value 625
Units C/W
Notes:
1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150C. 2.Pulse width <300us, duty cycle <2%. 3.Mounted on FR4 board
11/26/2005 Rev.3.01
www.SiliconStandard.com
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SSM7002DGU
ELECTRICAL CHARACTERISTICS
Symbol BVDSS Parameter Drain-source breakdown voltage
(at Tj = 25C, unless otherwise specified)
Test Conditions VGS=0V, ID=10uA Min. 50 Typ. Max. Units V
ID(ON)
RDS(ON)
On-state drain current
Static drain-source on-resistance
VDS= 7V, VGS=10V
VGS=10V, ID =250mA VGS=5V, ID =50mA
500
1 80 -
-
3 4 2.5 1.0 100
mA
V mS uA nA
VGS(th) gfs IDSS IGSS
Gate threshold voltage Forward transconductance
VDS=VGS, ID=250uA VDS=7V, ID=200mA
Drain-source leakage current
Gate-source leakage current
VDS=50V, VGS=0V
VGS=20V
td(on) tr td(off) tf Ciss Coss Crss
Turn-on delay time 2 Rise time Turn-off delay time Fall time Input capacitance Output capacitance Reverse transfer capacitance
VDS=30V ID=100mA RG=10 , VGEN=10V VGS=0V VDS=25V f=1.0MHz
-
7.5 6 7.5 3 19 10 3
20 20 50 25 5
ns ns ns ns pF pF pF
Source-Drain Diode
Symbol VSD Parameter Forward voltage
2
Test Conditions IS=115mA, VGS=0V
Min. -
Typ. 0.76
Max. Units 1.5 V
Notes:
1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150C. 2.Pulse width <300us, duty cycle <2%.
11/26/2005 Rev.3.01
www.SiliconStandard.com
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SSM7002DGU
Drain Current (A)
Drain to source voltage (V)
Drain Current (A)
Gate to source voltage (V)
Fig 1. Typical output characteristics
Fig 2. Typical transfer characteristics
Drain to source resistance ( ))
Capacitance (pF)
Drain to source voltage (V)
Drain current (A)
Fig 3. Typical Capacitance
Fig 4. Normalized on-resistance vs. junction temperature
Gate source threshold voltage (V) -
Source-drain Current (A)
Body diode forward voltage (V)
Junction temperature (C)
Fig 5. Forward characteristics of the reverse diode
11/26/2005 Rev.3.01
Fig 6. Gate threshold voltage vs. junction temperature
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SSM7002DGU
Gate -source voltage (V)
Transconductance (S)
Total gate charge (nC)
Drain to source current (A)
Fig 7. Gate charge characteristics
Fig 8. Typical transconductance
Drain Current (A)
Drain-source voltage (V)
Fig 9. Maximum safe operating area
Transient thermal impedance r(t)
Square wave pulse duration (S)
Fig 10. Normalized Transient Thermal Impedance
11/26/2005 Rev.3.01
www.SiliconStandard.com
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PHYSICAL DIMENSIONS
SSM7002DGU
PHYSICAL DIMENSIONS
SOT-363
DIM A A1 bp C D E e e1 He Lp Q W
SOT-363 DIMENSION MILLIMETERS INCHES MIN MAX MIN MAX 0.80 1.10 0.031 0.043 -0.10 -0.004 0.10 0.30 0.004 0.012 0.10 0.25 0.004 0.010 1.80 2.20 0.071 0.087 1.15 1.35 0.045 0.053 1.30 (typ) 0.052 (typ) 0.65 (typ) 0.026(typ) 2.00 2.20 0.079 0.087 0.10 0.3 0.004 0.012 0.20 (typ) 0.008 (typ) 0.20 (typ) 0.008 (typ) 10o (typ) 10o (typ)
PACKING: Moisture sensitivity level MSL3
3000 pcs in antistatic tape on a reel packed in a moisture barrier bag (MBB).
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties.
11/26/2005 Rev.3.01
www.SiliconStandard.com
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